Semiconductor integrated circuits may include fusible conductive links, (i.e., fuses), which may be removed by irradiation using laser light. For example, in semiconductor memories such as dynamic random access memories (DRAMs), static random access memories (SRAMs), electrically erasable and programmable read only memories (EEPROMs) and so on, defective memory cells can be replaced by blowing fuses associated with them and allowing spare memory cells to be selected instead of the defective memory cells. Such a replacement technique, (i.e., a redundancy technique) may be accomplished by blowing fuses to inactivate a row or column line, or a memory block of defective memory cells and to activate a row or column line, or a memory block of spare memory cells upon receipt of address signals designating the defective memory cells, to enhance the fabrication yield of semiconductor memories. These redundancy techniques are disclosed in U.S. Pat. Nos. 4,794,568, 4,829,480 and 5,297,085, all of which are assigned to the present assignee, the disclosures of which are hereby incorporated herein by reference.
Semiconductor memory chips (e.g., such as DRAMs) may embed electronic circuit devices for performing various modes of operation such as a static column mode, page mode, nibble mode and the like. If users require a particular mode of operation, fuses may be blown to inactivate the unwanted modes. Fuses may also be blown to select desired logic circuits in semiconductor integrated circuits.
Recent integrated circuits use multilevel metallization techniques including at least two or more stacked interlevel insulating layers and metal interconnection layers formed on each interlevel insulating layer so as to increase the integration density for a given chip area. The metal interconnection layers are interconnected with circuit devices on a semiconductor substrate or with other interconnection layers through metallic plugs filled in via holes therein. Conventionally, fuses are formed between a topmost interlevel insulating layer and an underlying interlevel insulating layer contiguous thereto. The topmost interlevel insulating layer which is commonly called a passivating layer may have grooves therein so that the fuses may be cut by application of laser beam energy. Fuses of polysilicon are disclosed in U.S. Pat. No. 5,241,212. However, the use of polysilicon fuses may not simplify the process of fabricating integrated circuits using multilevel metallization techniques.
A technique for forming metal fuses such as aluminum fuses is disclosed in U.S. Pat. No. 5,185,291. As disclosed therein, a first layer of aluminum material is deposited on a dielectric surface and then etched locally to form holes or windows at one or several points selected for fusing, exposing the underlying dielectric. A second layer of aluminum material is deposited and then etched to produce a desired conductive path passing through such points. Thus, laser programmable fuse links may have locally reduced thickness at those points. However, glassy surfaces of aluminum fuse links may absorb only a small amount of the impinged laser energy. This means that high energy lasers may be required to severe the fuses. Moreover, using high energy laser light may result in a large amount of the energy being reflected from uneven surfaces of the fuse links or conductive paths, such as surfaces having hillocks or spikes, and may damage an interlevel insulating layer surrounding the fuse links. Such damage may create extensive cracks reaching adjacent metal interconnects or fuse links through the interlevel insulating layer. When these interconnects or fuse links are so exposed, they may become subject to corrosion which may subsequently result in the fuse or interconnect breaking. Thus, it is desired that the fuses can be readily severed using low level laser energy.
On the other hand, it may be required that metal fuse links and interconnects be simultaneously formed on the same insulating layer in a high density integrated circuit. When the metal interconnects are disposed at narrow spacings (e.g., sub-half micron) it may be difficult to make fine etching mask patterns for forming the metal interconnects due to optical light reflection into a photoresist layer from highly reflective surfaces of the metal interconnect layer. The failure of fine etching mask patterns may cause inadvertent shorts or opens in the interconnects. Particularly, the widths of the interconnects may be smaller than desired due to the failure of fine etching mask patterns. Increased current density may also be generated by forcing the same current through the smaller interconnects which may result in increased electro-migration of aluminum atoms (i.e., metal migration) which may cause the interconnects to become opened. The fuse links may also be susceptible to increased current densities, which tend to exacerbate electro-migration defects.
Thus, notwithstanding the above described techniques, there continues to be a need for improved methods of utilizing and forming fuse links.